ncsim> run
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_root.svh(392) @ 0: reporter [UVM/RELNOTES] 
----------------------------------------------------------------
UVM-1.2
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [RNTST] Running test test_1011...
UVM_INFO testbench.sv(149) @ 90: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 110: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 130: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 150: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 170: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 190: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 210: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 230: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 250: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 270: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 290: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b0
UVM_INFO testbench.sv(149) @ 310: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1
UVM_INFO testbench.sv(149) @ 330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 350: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 390: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 410: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 430: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 450: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 470: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 490: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 530: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 550: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 570: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 590: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 610: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 610: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 630: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 650: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 670: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 690: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 710: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 730: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 750: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 770: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 790: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 810: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 830: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 850: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 870: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 890: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 910: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 950: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 970: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 1010: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 1030: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 1050: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 1050: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 1070: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 1070: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 1090: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 1110: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 1130: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 1150: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 1170: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 1170: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 1190: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 1190: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 1210: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1230: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1250: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1270: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1290: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1310: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1350: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1390: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1410: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1430: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 1450: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 1470: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 1470: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 1490: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 1510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1530: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1550: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1570: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1590: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1610: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1650: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1670: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 1690: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 1710: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 1730: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 1750: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 1770: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1790: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1810: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1830: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1850: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 1870: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 1890: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 1910: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 1930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 1950: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 1950: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 1970: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 1970: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 1990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2010: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 2030: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 2050: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 2070: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 2090: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 2090: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 2110: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 2110: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 2130: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2150: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 2170: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 2190: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 2210: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 2230: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 2230: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 2250: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 2250: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 2270: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2290: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 2310: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 2330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 2330: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 2350: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 2370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2390: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 2410: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 2430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 2430: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 2450: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 2470: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2490: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2530: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2550: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 2570: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 2590: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 2590: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 2610: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 2630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2650: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2670: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2690: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2710: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2730: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2750: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2770: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 2790: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 2810: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 2810: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 2830: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 2850: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2870: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2890: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2910: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2950: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2970: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 2990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3010: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 3030: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 3050: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 3050: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 3070: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 3090: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3110: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3130: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3150: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3170: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 3190: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 3210: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 3230: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 3250: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 3270: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3290: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3310: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3350: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 3370: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 3390: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 3410: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 3430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 3450: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3470: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3490: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3530: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 3550: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 3570: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 3570: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 3590: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 3610: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3650: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3670: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3690: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3710: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 3730: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 3750: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 3770: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b100
UVM_INFO testbench.sv(149) @ 3790: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 3810: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b10
UVM_INFO testbench.sv(149) @ 3830: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 3850: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 3850: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 3870: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 3890: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3910: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3950: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 3970: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 3990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4010: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 4030: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 4050: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4050: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4070: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 4070: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 4090: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4110: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 4130: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4150: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4150: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4170: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 4190: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 4210: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4230: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4230: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4250: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b110
UVM_ERROR testbench.sv(156) @ 4250: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 4270: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4290: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4290: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4310: uvm_test_top.e0.sb0 [SCBD] in=0 out=1 ref=0b1011 act=0b110
UVM_INFO testbench.sv(149) @ 4330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4350: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4350: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 4370: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 4390: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4410: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 4430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4450: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4450: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4470: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 4490: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4530: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4550: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4570: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4590: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4610: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 4630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4650: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4650: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4670: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 4690: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 4710: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 4730: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4750: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4750: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4770: uvm_test_top.e0.sb0 [SCBD] in=0 out=1 ref=0b1011 act=0b110
UVM_INFO testbench.sv(149) @ 4790: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4810: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4810: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4830: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b110
UVM_ERROR testbench.sv(156) @ 4830: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 4850: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4870: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4870: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4890: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 4910: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 4930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 4950: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 4950: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 4970: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 4970: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 4990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5010: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 5030: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 5050: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 5070: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 5090: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 5090: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 5110: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 5110: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 5130: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5150: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5170: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5190: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 5210: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 5230: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 5250: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b10
UVM_INFO testbench.sv(149) @ 5270: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b100
UVM_INFO testbench.sv(149) @ 5290: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 5310: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b10
UVM_INFO testbench.sv(149) @ 5330: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b100
UVM_INFO testbench.sv(149) @ 5350: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 5370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 5390: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 5410: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5450: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5470: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5490: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 5510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 5530: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 5530: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 5550: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 5570: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5590: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5610: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5650: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 5670: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 5690: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 5710: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 5730: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 5750: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5770: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5790: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5810: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5830: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 5850: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 5870: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 5890: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 5910: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 5930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5950: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5970: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 5990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6010: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 6030: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 6050: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 6050: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 6070: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 6090: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6110: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6130: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6150: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6170: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6190: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 6210: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 6230: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 6250: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b100
UVM_INFO testbench.sv(149) @ 6270: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 6290: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b10
UVM_INFO testbench.sv(149) @ 6310: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 6330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 6330: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 6350: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 6370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6390: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6410: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6450: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 6470: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 6490: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 6510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 6530: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 6530: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 6550: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 6550: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 6570: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6590: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 6610: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 6630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 6630: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 6650: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 6670: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 6690: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 6710: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 6710: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 6730: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b110
UVM_ERROR testbench.sv(156) @ 6730: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 6750: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 6770: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 6770: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 6790: uvm_test_top.e0.sb0 [SCBD] in=0 out=1 ref=0b1011 act=0b110
UVM_INFO testbench.sv(149) @ 6810: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 6830: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 6830: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 6850: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 6850: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 6870: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 6890: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 6910: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 6930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 6950: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 6970: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 6990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7010: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 7030: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 7050: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 7050: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 7070: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 7090: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 7110: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 7130: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 7150: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 7170: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 7190: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7210: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7230: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7250: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 7270: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 7290: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 7290: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 7310: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 7330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7350: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 7370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 7390: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 7390: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 7410: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 7430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7450: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7470: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7490: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7510: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 7530: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 7550: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 7550: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 7570: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 7590: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7610: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7650: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7670: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7690: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7710: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7730: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7750: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7770: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7790: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7810: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7830: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7850: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7870: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7890: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 7910: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 7930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 7930: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 7950: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 7970: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 7990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8010: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8030: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8050: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8070: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8090: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8110: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8130: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8150: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8170: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8190: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 8210: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 8230: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 8250: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b10
UVM_INFO testbench.sv(149) @ 8270: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b100
UVM_INFO testbench.sv(149) @ 8290: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 8310: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b11
UVM_INFO testbench.sv(149) @ 8330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 8350: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8390: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8410: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 8430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 8450: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 8450: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 8470: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 8490: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8530: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 8550: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 8570: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 8590: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 8610: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 8610: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 8630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 8630: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 8650: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8670: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8690: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8710: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8730: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8750: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8770: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8790: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8810: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8830: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8850: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 8870: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 8890: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 8910: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1010
UVM_INFO testbench.sv(149) @ 8930: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 8950: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 8950: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 8970: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b111
UVM_ERROR testbench.sv(156) @ 8970: uvm_test_top.e0.sb0 [SCBD] ERROR ! out=0 exp=1
UVM_INFO testbench.sv(149) @ 8990: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9010: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9030: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 9050: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1101
UVM_INFO testbench.sv(149) @ 9070: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 9070: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 9090: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 9110: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9130: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9150: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9170: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1110
UVM_INFO testbench.sv(149) @ 9190: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b1100
UVM_INFO testbench.sv(149) @ 9210: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 9230: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b10
UVM_INFO testbench.sv(149) @ 9250: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b100
UVM_INFO testbench.sv(149) @ 9270: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1001
UVM_INFO testbench.sv(149) @ 9290: uvm_test_top.e0.sb0 [SCBD] in=0 out=0 ref=0b1011 act=0b10
UVM_INFO testbench.sv(149) @ 9310: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b101
UVM_INFO testbench.sv(149) @ 9330: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1011
UVM_INFO testbench.sv(166) @ 9330: uvm_test_top.e0.sb0 [SCBD] Pattern found to match, next out should be 1
UVM_INFO testbench.sv(149) @ 9350: uvm_test_top.e0.sb0 [SCBD] in=1 out=1 ref=0b1011 act=0b111
UVM_INFO testbench.sv(149) @ 9370: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9390: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9410: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9430: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9450: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(45) @ 9450: uvm_test_top.e0.a0.s0@@seq [SEQ] Done generation of 459 items
UVM_INFO testbench.sv(149) @ 9470: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9490: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9510: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9530: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9550: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9570: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9590: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9610: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO testbench.sv(149) @ 9630: uvm_test_top.e0.sb0 [SCBD] in=1 out=0 ref=0b1011 act=0b1111
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 9650: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 9650: reporter [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :  527
UVM_WARNING :    0
UVM_ERROR :   16
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[SCBD]   539
[SEQ]     1
[TEST_DONE]     1
[UVM/RELNOTES]     1

Simulation complete via $finish(1) at time 9650 NS + 59
/playground_lib/uvm-1.2/src/base/uvm_root.svh:517     $finish;
ncsim> exit