The SystemVerilog standard specifies that signals in a design possess both a type and a data type. The type designates whether the signal is a net or a variable, while the data type defines the value system of that net or variable which are 0, 1, X and Z.
4-state Data Types
Types that can have unknown (X) and high-impedance (Z) value in addition to zero (0) and one (1) are called 4-state types. In Verilog, all nets (eg. wire) and variables (eg. reg) use 4-state values. Note that reg can only be driven in procedural blocks like always and initial while wire can only be used in assign statements.
logic
SystemVerilog introduces a new 4-state data type called logic that can be driven in both procedural blocks and continuous assign statements. However, a signal with more than one driver needs to be declared a net-type such as wire so that SystemVerilog can resolve the final value based on strength.
module tb;
logic [3:0] my_data; // Declare a 4-bit logic type variable
logic en; // Declare a 1-bit logic type variable
initial begin
$display ("my_data=0x%0h en=%0b", my_data, en); // Default value of logic type is X
my_data = 4'hB; // logic datatype can be driven in initial/always blocks
$display ("my_data=0x%0h en=%0b", my_data, en);
#1;
$display ("my_data=0x%0h en=%0b", my_data, en);
end
assign en = my_data[0]; // logic datatype can also be driven via assign statements
endmodule
ncsim> run my_data=0xx en=x my_data=0xb en=x my_data=0xb en=1 ncsim: *W,RNQUIE: Simulation is complete.
