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SystemVerilog Disable Constraints

All constraints are by default enabled and will be considered by the SystemVerilog constraint solver during randomization. A disabled constraint is not considered during randomization.

Constraints can be enabled or disabled by constraint_mode().

Syntax

constraint_mode() can be called both as a task and as a function.

When called as a task, the method does not return anything. The task is supplied with an input argument to either turn on or off the given constraint. When called as a function, the method returns the current state of the given constraint.


// Called as a task
class_obj.const_name.constraint_mode(0); 			// Turn off the constraint
class_obj.const_name.constraint_mode(1); 			// Turn on the constraint
	
// Called as a function
status = class_obj.const_name.constraint_mode(); 	// status is an int variable to hold return value

constraint_mode() is a built-in method and cannot be overriden !

Read more: SystemVerilog Disable Constraints

SystemVerilog Inline Constraints

Consider that a class already has well written constraints and there is a need to randomize the class variables with a set of different constraints decided by the user. By using the with construct, users can declare in-line constraints at the point where the randomize() method is called. These additional constraints will be considered along with the object's original constraints by the solver.

Example


class Item;
  rand bit [7:0] id;
  
  constraint c_id { id < 25; }
  
endclass

module tb;
  
  initial begin
    Item itm = new ();
    itm.randomize() with { id == 10; }; 		// In-line constraint using with construct
    $display ("Item Id = %0d", itm.id);
  end
endmodule

Read more: SystemVerilog Inline Constraints

SystemVerilog pre_randomize & post_randomize

Variables that are declared as rand or randc inside a class are randomized using the built-in randomize() method. The method returns 1 if randomization was successful, and 0 if it failed. It can fail due to a variety of reasons like conflicting constraints, solver could not come up with a value that meets all constraints and such. Class objects are not randomized automatically, and hence we should always call the randomize() method to do randomization.

Syntax


	virtual function int randomize ();

Let's look at a simple example to see how randomize() can be called.


class Beverage;
  rand bit [7:0]	beer_id;
  
  constraint c_beer_id { beer_id >= 10;
                        beer_id <= 50; };
  
endclass

module tb;
   Beverage b;
    
    initial begin
      b = new ();
      $display ("Initial beerId = %0d", b.beer_id);
      if (b.randomize ()) 
      	$display ("Randomization successful !");
      $display ("After randomization beerId = %0d", b.beer_id);
    end
endmodule

Read more: SystemVerilog pre_randomize & post_randomize

SystemVerilog Associative Array

When size of a collection is unknown or the data space is sparse, an associative array is a better option. Associative arrays do not have any storage allocated until it is used, and the index expression is not restricted to integral expressions, but can be of any type.

An associative array implements a look-up table of the elements of its declared type. The data type to be used as an index serves as the lookup key and imposes an ordering.

Syntax


	// Value     Array_Name          [ key ];
	data_type    array_identifier    [ index_type ];

Initialization Example


module tb;
  	
	int   	array1 [int]; 			// An integer array with integer index
	int   	array2 [string]; 		// An integer array with string index
	string  array3 [string]; 		// A string array with string index
  
  	initial begin
      	// Initialize each dynamic array with some values
    	array1 = '{ 1 : 22,
	            	6 : 34 };
	            
		array2 = '{ "Ross" : 100,
	            	"Joey" : 60 };
	            
		array3 = '{ "Apples" : "Oranges",
	            	"Pears" : "44" };
      
      	// Print each array
      $display ("array1 = %p", array1);
      $display ("array2 = %p", array2);
      $display ("array3 = %p", array3);
    end
endmodule
 Simulation Log
ncsim> run
array1 = '{1:22, 6:34}
array2 = '{"Joey":60, "Ross":100}
array3 = '{"Apples":"Oranges", "Pears":"44"}
ncsim: *W,RNQUIE: Simulation is complete.

Read more: SystemVerilog Associative Array

SystemVerilog Dynamic Array

A dynamic array is an unpacked array whose size can be set or changed at run time, and hence is quite different from a static array where the size is pre-determined during declaration of the array. The default size of a dynamic array is zero until it is set by the new() constructor.

Syntax

A dynamic array dimensions are specified by the empty square brackets [ ].


	[data_type] [identifier_name]  [];

	bit [7:0] 	stack []; 		// A dynamic array of 8-bit vector
	string 		names []; 		// A dynamic array that can contain strings 

The new() function is used to allocate a size for the array and initialize its elements if required.

Dynamic Array Example


module tb;
	// Create a dynamic array that can hold elements of type int
	int 	array []; 			
	
	initial begin
		// Create a size for the dynamic array -> size here is 5
		// so that it can hold 5 values
		array = new [5]; 			
      
		// Initialize the array with five values
		array = '{31, 67, 10, 4, 99};
      
		// Loop through the array and print their values
		foreach (array[i]) 
			$display ("array[%0d] = %0d", i, array[i]);
	end
endmodule
 Simulation Log
ncsim> run
array[0] = 31
array[1] = 67
array[2] = 10
array[3] = 4
array[4] = 99
ncsim: *W,RNQUIE: Simulation is complete.

Read more: SystemVerilog Dynamic Array

  1. SystemVerilog Queue
  2. SystemVerilog 'unique' and 'priority' case
  3. Connecting register env
  4. SystemVerilog Modport
  5. SystemVerilog Interface Bundles

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