Funvizeo logo
  • Contents
      • Back
      • Verilog
      • SystemVerilog
      • UVM
      • Digital Basics
      • Verification
Most Popular
Verification
  Testbench Evolution
  Constraint Random Verification
  Verification Techniques
  Verification Plan
  Code Coverage

Verilog
  Data Types
  Basic Constructs
  Behavioral Modeling
  Gate Modeling
  Simulation Basics
  Design Examples
  Interview Questions

SystemVerilog
  Data Types
  Class
  Interface
  Constraints and more!
  Testbench Examples
  Interview Questions

UVM
  Sequences
  Testbench Components
  TLM Tutorial
  Register Model Tutorial
  Testbench Examples
  Interview Questions

Digital Fundamentals
  Binary Arithmetic
  Boolean Logic
  Karnaugh Maps
  Combinational Logic
  Sequential Logic

Verilog Interview Questions Set 10

  1. What logic is inferred when there are multiple assign statements targeting the same wire for synthesis ?

What logic is inferred when there are multiple assign statements targeting the same wire for synthesis ?

The synthesis tool will give a syntax error for a wire that is an output port of a module if it is driven by more than one source.


wire out;

assign out = a & b; 

// Elsewhere in the code, another assign to 
// the same wire will cause multiple driver error
assign out = a | b;

Read more: Verilog Interview Questions Set 10

Synchronous FIFO

  1. What is a synchronous FIFO ?

What is a synchronous FIFO ?

A synchronous FIFO (First-In-First-Out) is a type of data buffer used in digital systems that operates under a single clock domain, meaning both read and write operations occur using the same clock signal. This design ensures that data is processed in the order it was received, which is critical for maintaining data integrity in various applications.

A synchronous FIFO is called "synchronous" because it uses synchronized clocks to control the read and write operations. The read and write pointers of the FIFO are updated synchronously with the clocks, and data is transferred between the FIFO and the external circuit synchronously with the clocks.

sync fifo

Synchronous FIFOs are primarily used to buffer data when the rate of data transfer exceeds the rate of data processing. This is particularly important in high-speed systems where timing discrepancies can lead to data loss or corruption.

Read more: Synchronous FIFO

Verilog Binary to Gray

Gray code is a binary code where each successive value differs from the previous value by only one bit.

Implementation #1


module bin2gray #(parameter N=4) ( input  [N-1:0] bin, 
                                   output [N-1:0] gray);
  
  genvar i;    
  generate
    for(i = 0; i < N-1; i = i + 1) begin
      assign gray[i] = bin[i] ^ bin[i+1];
    end
  endgenerate
  
  assign gray[N-1] = bin[N-1];
endmodule

Read more: Verilog Binary to Gray

Gray Code

Gray code, also known as Gray binary code or reflected binary code, is a binary numeral system where adjacent values differ by only one bit. In other words, Gray code is a binary code where each successive value differs from the previous value by only one bit.

For example, the binary representation of decimal numbers 1 and 2 is 0001 and 0010 respectively. Note that two LSB bits (bit#0 and bit#1) have to change for the transition from 1 to 2. In Gray code, 1 and 2 are represented by 0001 and 0011 respectively but the same transition now requires only a change of one bit (bit#1 from LSB).

Read more: Gray Code

Shift Register

A shift register is a sequential digital circuit that is used to store and transfer binary data. It consists of a series of flip-flops connected in a chain, with each flip-flop holding a single bit of data. The input data is shifted through the register one bit at a time, either left or right, depending on the design.

Read more: Shift Register

  1. T Flip-Flop
  2. JK Flip-Flop
  3. D Flip-Flop
  4. SR Latch Circuit
  5. Sequential Logic

Page 11 of 68

  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
Interview Questions
  Verilog Interview Set 1
  Verilog Interview Set 2
  Verilog Interview Set 3
  Verilog Interview Set 4
  Verilog Interview Set 5

  SystemVerilog Interview Set 1
  SystemVerilog Interview Set 2
  SystemVerilog Interview Set 3
  SystemVerilog Interview Set 4
  SystemVerilog Interview Set 5

  UVM Interview Set 1
  UVM Interview Set 2
  UVM Interview Set 3
  UVM Interview Set 4
Related Topics
  Digital Fundamentals
  Verilog Tutorial

  Verification
  SystemVerilog Tutorial
  UVM Tutorial
Latest in Verilog
  • Verilog $random
  • Verilog VCD Dump
  • Verilog VCD
  • Verilog Namespace
  • Verilog $stop $finish
Latest in SystemVerilog
  • SystemVerilog `define Macro
  • SystemVerilog Callback
  • SystemVerilog Interview Questions Set 10
  • SystemVerilog Interview Questions Set 9
  • SystemVerilog Interview Questions Set 8
Latest in UVM
  • UVM Callback
  • UVM Singleton Object
  • UVM Component [uvm_component]
  • UVM Object [uvm_object]
  • UVM Root [uvm_root]
© 2025 Funvizeo
Terms and Conditions