Verilog Interview Questions Set 11

What are the considerations to be taken choosing between flop-flops vs. latches in a design?

1. Functional requirements: The first consideration is the functional requirements of the system. Different types of flip-flops and latches have their specific functions and capabilities, and it is necessary to choose the appropriate type based on the system's requirements.
2. Timing requirements: Flip-flops have a fixed clock edge at which they latch the data, while latches hold the data as long as the enable signal is active. Latches facilitate time borrowing or cycle stealing, and helps increase pipeline depth with lesser area.
3. Power consumption: Flip-flops tend to consume more power than latches, as they operate continuously with a clock signal. If power consumption is a concern, latches may be preferred.
4. Noise immunity: Flip-flops are more immune to noise than latches since they latch their values at a specific clock edge. If the design has a lot of noise, flip-flops may be the better option.
5. Area and cost: Latches are typically smaller and less expensive than flip-flops. If the design needs to optimize for area or cost, latches may be preferred.
6. Operating frequency: With time borrowing and cycle stealing, operating frequency is higher than the slowest logic path for latch. But in the case of FF, the slowest path pretty much decides the operating frequency.

Read more on Sequential Logic.

Which one is better, asynchronous or synchronous reset for the storage elements?

• Reset signal is not part of the data path in async-reset whereas reset signal is part of the D input of the FF in sync-reset.
• Effect of reset can happen anytime in async-reset whereas effect of reset will happen only on the active edge of a clock in sync-reset.
• Async-reset is prone to glitches where as sync-resets are safer in this regard.
• Async-reset needs to meet only the minimum reset pulse width for FF where as sync-reset has to be long enough to be sampled on the next clock edge.
• Async-reset input still needs the double FF synchronization to avoid race condition during reset de-assertion, while sync-reset do not need such additional circuitry.

What logic gets synthesized when integer is used instead of a reg variable as a storage element?

When an integer is used as a storage element in a Verilog RTL code, it gets synthesized as a block of flip-flops similar to when a reg variable is used. Note that synthesis tool will optimize and remove unused flops.

module design (...);
	integer 	tmp;
	reg [7:0] 	data;

	always @ (posedge clk) begin
		// tmp [31:8] will be optimized because it is unused
		// since width of "data" is only 8b and so "tmp" does
		// not ever need anything more than 8b.
		tmp <= data; 	
	end
endmodule

However, the encoding and implementation of the flip-flops may differ between integers and regs, and this may affect the timing, area, and power consumption of the design. reg the recommended storage element for most RTL designs, as they are optimized for sequential logic operations and have predictable timing, area, and power consumption characteristics.

Read more on Verilog Data Types.

How do I choose between a case statement and a multi-way if-else statement?

A case statement should be chosen to implement a multiplexer, whereas a multi-way if-else statement should be chosen to implement a priority encoder.

Note that if the default clause is missing in a case statement or all the possible cases are not specified then a latch is inferred. Similarly, for an if-else construct, a missing final else clause will infer a latch.

Read more on Verilog case and if-else-if statements.

How do I avoid a priority encoder in an if-else tree?

The SystemVerilog keyword unique can be used which indicates that the order of decisions is not important and it would synthesize into parallel logic or multiplexer.

unique if (in[0]) sel = 0;
else if (in[1]) sel = 1;
else sel = 2;

Read more on SystemVerilog 'unique' and 'priority' case.

What are the differences between if-else and the ?: conditional operator?

• Conditional operator is typically used in continuous assignments while if-else is used within procedural blocks.
• A true and false expression is always required for the conditional operator whereas else part is optional in the if construct.
• Conditional operators cannot have block statements with begin and end whereas if conditions can.

• Deeply nested conditional expressions are harder to understand whereas if statements are cleaner in this regard.

Read more on Verilog Conditional Statements.

What is the importance of a default clause in a case construct?

The default clause is executed when none of the other cases are satisfied and if this is missing the logic will have to remember what the earlier value was and hence synthesis will infer a latch.

What is the difference between full_case and parallel_case synthesis directive?

Read more on Verilog case statement.

What is the difference in implementation with sequential and combinatorial processes, when the final else clause in a multiway if-else construct is missing?

In a sequential process, if the final else clause is missing, the synthesis tool will generate a synthesis warning or error since it indicates a missing case. This is because, in a sequential process, when the state machine is in a particular state, it must always navigate to a subsequent state. An incomplete if-else statement violates this requirement and could lead to unpredictable behavior in sequential circuits. Therefore, it is essential to add a final else clause that catches all cases, explicitly updating the state or initiating a defined process before it returns to the beginning to avoid unexpected behavior.

In contrast, in a combinatorial process, the absence of a final else clause is not considered an error since the logic is always evaluated and computed afresh without relying on any past history or state. The expression is evaluated continuously and only depends on the values of the inputs to the expression. The synthesis tool will infer a latch or memory element to store the previous value, and it uses this to calculate the output at each step.

What is the difference in using (== or !=) vs. (=== or !==) in decision making of a flow control construct in a synthesizable code?

Only logical equality/inequality operators (== and !=) are synthesizable. Case equality (===) and inequality (!==) operators also compare X and Z values, whereas result is always false for logical comparison.

When both operands have unknown or high-impedance state 'x' as one of the bits, the regular equality and inequality operators will return 0, indicating a false result. However, in case operators, this comparison will generate an 'x' or unassigned, indicating that the inputs are not predictable.

// If a or b has X/Z values (in addition to a!=b), 
// out will be driven a OR b
if (a == b) 
   	out = a & b; 	
else
	out = a | b;


// Both a and b match is done for 4-states
// out = a AND b only when a/b are both 0, 1, X or Z
if (a === b) 
	out = a & b;
else
	out = a | b;