Verilog Timing Checks

What are timing checks ?

Timing checks in digital design are critical for ensuring that a circuit meets its specified timing requirements. They help verify that signals propagate through the circuit within the allowed time constraints, preventing issues such as setup and hold time violations.

Timing checks must be placed inside a specify block in a Verilog module.

specify
  // Timing check statements
endspecify

What are reference and data events ?

All timing checks involve a reference event and a data event, each of which can be associated with boolean conditions.

The reference event is a signal transition that establishes a point in time for measuring other events. It is typically associated with clock edges (e.g., posedge or negedge) or other significant control signals. For example, in a setup time check, the reference event would be the rising edge of a clock signal.

The data event is the signal whose timing is being monitored relative to the reference event. This signal typically represents data inputs to registers or flip-flops. For instance, in a hold time check, the data event would be the stable state of a data signal immediately following the clock edge defined by the reference event.

specify
    $setup(data_signal, posedge clk, setup_time_limit);     // posedge clk is reference event
    $hold(posedge clk, data_signal, hold_time_limit);       // data_signal is the data event
endspecify

Timing checks will only detect reference and data events when their corresponding conditions are satisfied.

What are timestamp and timecheck events ?

The evaluation of timing checks relies on the times of two events, referred to as the timestamp event and the timecheck event.

When there is a transition on the timestamp event signal, the simulator records (or "stamps") the time of that transition for later use in assessing the timing check. Conversely, a transition on the timecheck event signal prompts the simulator to evaluate the timing check to determine if a violation has occurred.

Example

In the classic example below illustrating a setup condition, the reference event corresponds to the rising edge of the clock at the capture edge, while the data event represents the arrival edge of FF2.D. The timestamp event is recorded when data arrives at FF2.D, and the timecheck event occurs at the rising edge of the clock.

$setup

It checks for setup time violations. A violation is reported if the time difference between the reference event and the data event is less than the specified limit.

The tool has to figure out a time window within which checks have to be done and is calculated as follows:

time_window_begin  = timecheck_time - limit
time_window_end    = timecheck_time

// Report violation if 
time_window_begin < timestamp_time < time_window_end

The data event is usually a data signal, while the reference event is usually a clock signal. When the limit is zero, $setup check will not issue a violation.

$setup(data_event, reference_event, limit[, notifier]);

$setup(data, posedge clk, 3);   // Example

$hold

It checks for hold time violations. A violation is reported if the data event occurs before the hold time after the reference event.

time_window_begin    = timestamp_time
time_window_end      = timestamp_time + limit

// Report a violation if
time_window_begin < time_check_time < time_window_end

The data event is usually a data signal, while the reference event is usually a clock signal. When the limit is zero, $hold check will not issue a violation.

$hold(reference_event, data_event, limit[, notifier]);

$hold(posedge clk, data, 5);    // Example

$setuphold

It combines setup and hold checks into one. Reports violations based on both setup and hold conditions.

$setuphold(reference_event, data_event, setup_limit, hold_limit[, notifier]);

$setuphold(posedge clk, data, 5, 10);   // Example

$recovery

It checks reset recovery violations. Reports a violation if the recovery time condition is not met.

time_window_begin    = timestamp_time          // reference event
time_window_end      = timestamp_time + limit 

// Report violation if
time_window_begin <= timecheck_time < time_window_end

The reference event is usually a control signal like clear or reset while the data event is usually a clock signal. When the limit is zero, $recovery check will not issue a violation.

$recovery(reference_event, data_event, limit[, notifier]);

$recovery(posedge clk, reset, 4);

$removal

Ensure that after a reset or significant change in state, the signal returns to its stable condition within an acceptable timeframe.

time_window_begin    = timecheck_time - limit   // reference event
time_window_end      = timecheck_time

// Report a violation if
time_window_begin < timestamp_time < time_window_end

The reference event is usually a control signal like clear or reset, while the data event is usually a clock signal.

$removal(reference_event, data_event, limit[, notifier]);

$removal(posedge clk, data_signal, 5);   // Example

$recrem

Combines recovery and removal checks into one.

$recrem(reference_event, data_event, rec_limit, rem_limit[, notifier]);

$recrem(posedge clk, data_signal, 5);    // Example