Verilog Interview Questions Set 14

What happens to the bits of a reg which are declared, but not assigned or used?

Bits that are unused are optimized away during synthesis.


module design (...);

reg [3:0] tmp;

always @ (posedge clk) begin
	if (! resetn) begin
		tmp <= 0;
                
	// Since tmp[1] and tmp[2] are unused,
    // synthesized logic will contain only 2 flops
	end else begin
    	tmp[0] <= in;
		tmp[3] <= ~in;
	end
end

endmodule

How does the generate construct help in optimal area ?

The generate construct is a feature that allows designers to create multiple instances of a module or block of code.

It allows the use of a variable using genvar keyword to control the generated logic. It can have for loop, if else or case statements inside it for conditional generation of replicated hardware.

How can you ensure the synthesizable Verilog will build a sequential logic ?

Use non-blocking assignments in always block triggered @ posedge clk
Use positive edge triggered FF for state
Do not assign the same variable in multiple always blocks
Keep sequential and combinational blocks separate
Do not mix blocking and non-blocking assignments in the same procedural block

Can the generate construct be nested?

No, the generate construct cannot be nested and will result in a syntax error if it is done so. But, if else, case conditional statements and for loops can be nested.


module design (...);

generate 
	...
	// Not allowed, results in error
	generate 
		...
	endgenerate
endgenerate

// Same module can have multiple independent
// generate blocks
generate 
...
endgenerate

generate
...
endgenerate

endmodule

What is a critical path in a design? What is the importance of understanding the critical path?

In a digital design, the critical path is the path of logic gates and interconnects that has the longest propagation delay, limiting the overall maximum operating frequency of the circuit. It is the slowest path of the combinational logic circuits that has the most significant impact on the performance of the design.

Accurately identifying the critical path is essential for timing analysis and avoiding timing violations, which can cause synchronization issues, glitches, or failures. Once the critical path is known, the designer can optimize it through techniques like pipelining, parallelism, or parallel paths to improve performance without affecting the design's functionality.

How does proper partitioning of design help in achieving static timing?

Partitioning the design refers to dividing a complex design into smaller sub-blocks that can be designed and analyzed separately to simplify the overall design.

Here are a few ways proper partitioning of a design can help:

Reduces the complexity of timing analysis: Breaking down the design into smaller sub-blocks reduces the complexity required for the Static Timing Analysis (STA) and enables timing closure, making it easier to identify and fix the bugs.
Enables parallel processing: Partitioned designs can be processed in parallel, thereby reducing the overall computation time. The designer can then optimize each sub-block independently for maximum utilization of computational resources.
Enables design reuse: Partitioning the design allows for the reuse of the smaller sub-blocks in different designs, leading to reduced development time and cost.
Reduces the critical path: Partitioning the design and optimizing each sub-block reduces their critical paths, ensuring multiple non-critical paths, which lowers the system's worst-case path delay and helps meet timing constraints.

What does it mean to "retime" logic between registers? How does it effect functionality?

Retiming is a technique used in digital circuit design to balance the path delay between sequential elements (registers) and combinational logic circuits. Retiming involves moving flip-flops so that the critical path is shifted to reduce its delay.

When correctly applied, retiming does not affect the functionality of the circuit. The circuit maintains its intended behavior, but the delay between the registers is redistributed, allowing for improvements in overall performance.

Why is one-hot encoding preferred for FSMs designed for high-speed designs?

One-hot encoding is a technique used to encode state bits of a Finite State Machine (FSM) such that only one state bit is high (1) for each state. This encoding method is particularly useful for high-speed FSM designs due to the following reasons:

Reduced delay and fast transition: In a one-hot encoded FSM, each state can be represented by a single flip-flop, and a change of state requires changing the output of only one flip-flop which reduces propagation delay and ensures fast state transition times.
Concurrent output generation: Each state corresponds to a unique output bit, so concurrent output generation is possible. This is because the current state can be determined without the propagation delay of a decoder, which enables faster clock speeds, improved throughput, and smaller critical paths.
Easier timing closure: It makes the design simpler and less prone to timing violations which results in an easier timing closure .
Reduced area and power consumption: Using a one-hot encoded FSM allows for easier implementation and requires fewer gates in the design, resulting in reduced area and power consumption.

What are the main factors that affect testability of a design?

Some factors include the presence of derived and gated clocks, latches and tri-state buses in the design.

My chip has on-chip tri-state buses. What are the testability implications, and how do I take care of it?

Tri-state buses allow multiple devices to share data lines while minimizing the capacitance and current requirements for each device. The key issue with testing tri-state buses is to ensure that any open or stuck gates associated with the tri-state buses can be identified and tested effectively. These faults can cause contention or isolation errors, leading to intermittent or erratic behavior of the chip.

Some ways to improve testability are:

Controlling the tri-state gates: To test the tri-state buses, it is essential to ensure that one device at a time is driving the bus. This can be achieved by controlling the tri-state gates and ensuring that all but one device is in the high-impedance state during the test.
Using built-in self-test (BIST) circuitry: BIST circuitry can be added to the design to control and isolate the tri-state buses for testing. BIST circuitry can be used to scan in test patterns that will isolate and exercise each tri-state gate within the design.