- Async resets of some FFs are driven by other FFs, how does this affect testability ?
- What are the testability implications for derived clocks ?
- What are the testability challenges of gated clocks ?
- What is the implication of a combinatorial feedback loops in design testability?
- How does the presence of latches affect the testability ?
- What value is sampled by the logic from an input port that is left open (that is, no-connect) during its module instantiation?
- How is the connectivity established in Verilog when connecting wires of different widths?
- Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?
- Summarize the main differences between $strobe and $monitor
- How can I selectively enable or disable monitoring?
Async resets of some FFs are driven by other FFs, how does this affect testability ?
During scan testing, if the driving FF gets a pattern such that it resets the driven FF, it will lose its data. Hence the reset output from the first FF should be OR'd with a test mode enable signal before assigning to the second FF.
What are the testability implications for derived clocks ?
Derived clocks are created within a chip using clock dividers through Flip-Flops or PLLs. Because these clocks are generated internally, a control signal from the primary pins is necessary to prevent Flip-Flops from capturing data at unintended times.
A multiplexor can be added in the clock path with the select line controlled by a test mode enable signal. The inputs to the mux should be regular clock and derived clock.
What are the testability challenges of gated clocks ?
Gated clocks are typically used to reduce power consumption by disabling the clock signal to specific parts of the chip when they are not in use. However, during testing, it is essential to be able to access and control these signals in order to ensure correct operation of the chip and detect any faults.
The workaround is to logically OR a test mode enable signal to the enabling pin of the AND gate that gates the clock.
What is the implication of a combinatorial feedback loops in design testability?
Combinatorial feedback loops occur when the output of a combinational logic gate is fed back into one of its inputs, potentially creating a feedback loop that can lead to unexpected behavior or cause the design to become stuck in an unstable state. Since the loops are delay-dependent, they cannot be tested with any ATPG algorithm and must be avoided in the logic.
How does the presence of latches affect the testability ?
One of the main issues with latches is that they can cause the propagation of glitches, which are short-lived pulses that can be difficult to observe during testing. These glitches can be especially problematic if they propagate to other parts of the design, potentially causing unintended behavior or creating false positives during testing.
Output of a latch is not controllable directly from a primary input since, the enable to a latch is not the regular clock going to rest of the flops in the design. The enable pin to the latch needs to be OR'd with a test mode enable signal.
What value is sampled by the logic from an input port that is left open (that is, no-connect) during its module instantiation?
An unconnected input port is a floating port, and it may float to an intermediate voltage level due to parasitic capacitance and inductance in the circuit. In simulations, this is indicated by the value 'Z' or high impedance and the logic following it will also propagate the 'Z' until gated off by an AND gate.
To avoid these types of issues, it is generally recommended to tie all unused input ports to a known state, such as ground or VDD, through the use of pull-up or pull-down resistors. This can help to prevent the input signal from floating and ensure that the logic gates are working as intended.
The default value of Z can be changed using compiler directives.
// Causes all unconnected input ports following this to be pulled down to logic 0
`unconnected_drive pull0
module mod_2341( ... );
...
endmodule
// Do not apply for rest of the code
`nounconnected_drive
How is the connectivity established in Verilog when connecting wires of different widths?
Connections are right-justified, which means that the LSB of the RHS is connected to the LSB of the LHS.
wire [7:0] net1;
wire [3:0] net2;
// net2 has smaller width than net1, and net1[7:4] is left floating
assign net1 = net2;
// net2 gets the truncated value of net1[3:0]
assign net2 = net1;
Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?
No, you cannot use a Verilog function to define the width of a multi-bit port, wire, or reg type. The width of a Verilog port, wire, or reg declaration must be a constant or a parameter value, both of which are determined at compile-time.
Functions, on the other hand, are executed at run-time and their return values cannot be used to dynamically set the widths of Verilog objects. Attempting to use a function to define the width of a port, wire, or reg will result in a compile-time error. However, you can use function parameters to define the width of Verilog objects. For example, you can declare a parameter and use it to specify the width of a port or signal as follows:
parameter WIDTH = 8;
input [WIDTH-1:0] input_signal; // Okay
input [find_width():0] input_signal; // Error
Summarize the main differences between $strobe and $monitor
$strobe displays values of selected signals at the end of the current simulation time when all simulation events have occurred and just before time advances whereas $monitor displays the value of selected signals whenever its value changes.
Read more on Verilog Display Tasks.
How can I selectively enable or disable monitoring?
This can be done with $monitoron and $monitoroff tasks.
